Add exercises

Exercises/.gitignore

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+*.v
+.idea/
+project/
+simWorkspace/
+target/
+tmp/

Exercises/build.sbt

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+name := "SpinalExercises"
+version := "0.1"
+
+scalaVersion := "2.11.12"
+val spinalVersion = "1.7.3"
+
+fork := true
+
+libraryDependencies ++= Seq(
+  "com.github.spinalhdl" % "spinalhdl-core_2.11" % spinalVersion,
+  "com.github.spinalhdl" % "spinalhdl-lib_2.11" % spinalVersion,
+  compilerPlugin("com.github.spinalhdl" % "spinalhdl-idsl-plugin_2.11" % spinalVersion)
+)

Exercises/src/main/scala/examples/Counter16.scala

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+package examples
+
+import spinal.core._
+
+class Counter16 extends Component {
+  val enable = in(Bool)
+  val counter = out(UInt(16 bits))
+
+  val lsb = new Counter8
+  lsb.enable := enable
+
+  val msb = new Counter8
+  msb.enable := enable && (lsb.counter === 0xff);
+
+  counter := msb.counter @@ lsb.counter
+}

Exercises/src/main/scala/examples/Counter8.scala

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+package examples
+
+import spinal.core._
+
+class Counter8 extends Component {
+  val enable = in(Bool)
+  val counter = out(Reg(UInt(8 bits)).init(0))
+
+  def count(): Unit = {
+    enable := True
+  }
+
+  when (enable) {
+    counter := counter + 1
+  }
+}

Exercises/src/main/scala/examples/Spi.scala

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+package examples
+
+import spinal.core._
+import spinal.lib._
+
+class SpiBus(numSlaves: Int = 1) extends Bundle with IMasterSlave {
+  val sclk = Bool
+  val mosi = Bool
+  val miso = Bool
+  val ss   = Bits(numSlaves bits)
+
+  override def asMaster(): Unit = {
+    out(sclk, mosi, ss)
+    in(ss)
+  }
+}
+
+class SpiMaster extends Component {
+  val bus = master(new SpiBus)
+}
+
+class SpiSlave extends Component {
+  val bus = slave(new SpiBus)
+}
+
+class Soc extends Component {
+  val spiMaster = new SpiMaster
+  val spiSlave = new SpiSlave
+  spiMaster.bus <> spiSlave.bus
+}

Exercises/src/main/scala/examples/Top.scala

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+package examples
+
+import spinal.core._
+import spinal.core.sim._
+
+object CounterGen {
+  def main(args: Array[String]): Unit = {
+    SpinalVerilog(new Counter16)
+  }
+}
+
+object CounterSim {
+  def main(args: Array[String]) {
+    SimConfig.withWave.compile(new Counter16).doSim {dut =>
+      dut.enable #= true
+
+      dut.clockDomain.forkStimulus(10)
+
+      var tick = 0
+
+      while (tick < 256 * 256) {
+        dut.clockDomain.waitSampling()
+        tick += 1
+      }
+    }
+  }
+}

Exercises/src/main/scala/exercises/Popcnt.scala

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+package exercises
+
+import spinal.core._
+
+class Popcnt(width: BitCount = 4 bits, multiCycle: Boolean = false) extends Component {
+  // Replace these by the correct I/O ports
+  val start, ready = Bool
+  val value, count = UInt(42 bits)
+
+  if (!multiCycle) {
+    // Implement asynchronous logic here.
+  } else {
+    // Implement multi-cycle logic here.
+  }
+}

Exercises/src/main/scala/exercises/ShiftReg.scala

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+package exercises
+
+import spinal.core._
+
+
+class ShiftReg extends Component {
+  def addReg(name: String, width: BitCount, delay: Int): (Bits, Bits) = {
+    (null, null)
+  }
+
+  def getReg(name: String): (Bits, Bits) = {
+    (null, null)
+  }
+}

Exercises/src/main/scala/exercises/Top.scala

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+package exercises
+
+import spinal.core._
+import spinal.core.sim._
+
+object PopcntSim {
+  def runSim(width: BitCount, multiCycle: Boolean, input: Int): Unit = {
+    SimConfig.withWave.compile(new Popcnt(width, multiCycle)).doSim {dut =>
+      dut.clockDomain.forkStimulus(10)
+
+      dut.value #= input
+      dut.start #= true
+      dut.clockDomain.waitSampling()
+      dut.start #= false
+
+      while (!dut.ready.toBoolean) {
+        dut.clockDomain.waitSampling()
+      }
+
+      dut.clockDomain.waitSampling()
+      println(s"popcnt($input) = ${dut.count.toBigInt}")
+    }
+  }
+
+  def main(args: Array[String]) {
+    runSim(4 bits, false, 15)
+  }
+}
+
+object ShiftRegSim {
+  def createShiftReg: ShiftReg = {
+    val sr = new ShiftReg
+    sr.addReg("foo", 8 bits, 3)
+    sr.addReg("bar", 16 bits, 5)
+    sr
+  }
+
+  def main(args: Array[String]) {
+    SimConfig.withWave.compile(createShiftReg).doSim {dut =>
+      dut.clockDomain.forkStimulus(10)
+
+      val (fooIn, fooOut) = dut.getReg("foo")
+      val (barIn, barOut) = dut.getReg("bar")
+
+      var tick = 0
+
+      while (tick < 10) {
+        fooIn #= tick
+        barIn #= 10 - tick
+        dut.clockDomain.waitSampling()
+        tick += 1
+      }
+    }
+  }
+}