Add exercises

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Job Noorman 2022-10-13 11:52:00 +02:00
commit ac3cf23632
19 changed files with 21160 additions and 0 deletions

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package spinaltest
import spinal.core._
import spinal.core.sim._
class Counter extends Component {
val count = out(Reg(UInt(8 bits)).init(0))
count := count + 1
}
object Gen {
def main(args: Array[String]) {
SpinalVerilog(new Counter)
}
}
object Sim {
def main(args: Array[String]) {
SimConfig.withWave.compile(new Counter).doSim {dut =>
dut.clockDomain.forkStimulus(10)
var tick = 0
while (tick < 10) {
dut.clockDomain.waitSampling()
tick += 1
}
println(s"counter: ${dut.count.toBigInt}")
}
}
}