111 lines
4.7 KiB
Markdown
111 lines
4.7 KiB
Markdown
# Introduction
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This exercise session introduces SpinalHDL, a Scala-based Hardware Description
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Language (HDL). SpinalHDL is implemented as a Scala library that generates RTL
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in the form of either Verilog or VHDL code. It is also capable of running, and
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interacting with, a Verilog simulation from Scala.
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SpinalHDL is a RTL code generator rather than a higher-level HDL. Of course, the
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full power of Scala can be used to build abstractions on top of the basic RTL
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components but only by combining those basic components. Having a good
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understanding of RTL is therefore imperative before using SpinalHDL.
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Before diving into this session, it is strongly recommended to read our
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[tutorial](Tutorial.md).
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# Exercises
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# 1. popcnt
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For the first exercise, the `popcnt` module mentioned during the Verilog lecture
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should be implemented in SpinalHDL. This module takes as input a bitvector, and
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returns the number of `1` bits in it.
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The end goal is to implement a class that is
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configurable in the number of bits of the input and in whether the operation
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should be implemented in multiple cycles. The logic should be implemented in
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`Popcnt.scala` and the simulation can be run using the `PopcntSim` object in
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`Top.scala`.
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The `Popcnt` component has the following constructor parameters:
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- `width`: the bit width of the input;
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- `multiCycle`: boolean indicating whether the logic should be implemented in
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multiple cycles or asynchronous.
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The following I/O ports should be defined by the `Popcnt` component:
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- `start` (input): asserted when the operation should start. Not needed for the
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asynchronous logic but should still be defined;
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- `value` (input): input to the operation;
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- `count` (output): result of the operation;
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- `ready` (output): asserted when the operation is ready. Not needed for the
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asynchronous logic but should still be defined;
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It is recommended to implement the logic incrementally:
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1. Implement the logic for a 4-bit asynchronous circuit. Beware that even though
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the operation should be implemented using purely combinational logic, the
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result should still be stored in a register. Also, the simulation will fail
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with an obscure error message if you try to run it before defining a register
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in your implementation;
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1. Generalize this logic to support arbitrary bit widths. Hint: one way to do
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this is to use a fold operation on the bits of the input;
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1. Add the logic for the multi-cycle implementation.
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You can run the tests by executing `sbt 'runMain exercises.PopcntSim'` in the
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Exercises directory. Look at the test cases and add more to thoroughly test your
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implementation!
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# 2. Configurable shift register
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In this exercise, you will be implementing a component that manages [shift
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registers](https://en.wikipedia.org/wiki/Shift_register). This component
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provides the following method to dynamically add a shift register:
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```scala
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def addReg(name: String, width: BitCount, delay: Int): (Bits, Bits)
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```
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This methods adds a new shift register to the component containing `delay`
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`width`-bit registers in cascade. The `name` argument can be used to generate
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readable names for all created I/O ports and registers. The return value of this
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method is a 2-tuple where the first element is an input connected to the first
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register in the cascade and the second element an output connected to the last.
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The method `getReg` should return the same tuple.
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As an example, the image below shows the configuration of the component after
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calling
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```scala
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addReg("foo", 8 bits, 3)|
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```
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In this case, the tuple returned would be `(foo_in, foo_out)`.
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SpinalHDL globally keeps track of the "current component". Whenever a new
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instance is created of a `Component` subclass, the current component is set to
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this instance. When logic is created, it is added to the current component. This
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means that if logic is created inside the `addReg` method, it will be added to
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the component that called this method, which is not what we want. To solve this,
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SpinalHDL offers the `rework` method which can be called on a `Component` to add
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logic to it after its creation:
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```scala
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class ExtendableComponent extends Component {
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def addLogic(): Unit = {
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rework {
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// Add logic here
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}
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}
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}
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```
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The logic for this exercise should be implemented in `ShiftReg.scala` and the
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simulation can be run using the `ShiftRegSim` object in `Top.scala`. The
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simulation adds two registers (see method `createShiftReg`) and runs for 10
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cycles, setting the input of the first register to increasing values starting at
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0, and the input of the second register to decreasing values starting at 10.
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Find the generated VCD file and examine it in GTKWave to confirm that your
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implementation works as expected.
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